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rej03f0268-0200 rev.2.00 mar 18, 2008 page 1 of 14 M66238FP standard clock generator with pll frequency synthesizer rej03f0268-0200 rev.2.00 mar 18, 2008 description the m66238 is a lsi that incorporates a pll synthesizer and a sync clock generator in it. the pll synthesizer covers the range of 25 mhz to 50 mhz at the minimum steps of 3 khz. the sync circuit outputs a clock and a one-shot pulse which ar e synchronized with an external trigger signal. setting a dividing ratio allows acquisition of sync clock outputs within the range of 0.78 mhz to 25 mhz. features ? sync clock output frequency range: 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 of 25 to 50 mhz ? sync accuracy (jitter): 3 ns ? trigger input: polarity selectable ? one-shot pulse output: polarity and width selectable ? 5 v power supply application pixel clock generator block diagram chip select input serial data input serial clock input clock input sin serial write control circuit crystal oscillator circuit vco 25 mhz to 50 mhz 15-bit counter command register command control circuit sync/divider circuit sync clock generator fvco 12-bit divider 12 15 phase comparator charge pump fin 3 4 5 7 6 2 17 21 up down cpout cpin rv pulse ckob tcko tcki clock output pll output test pin cko/ pllo one-shot pulse output 20 24 26 29 14 13 12 11 10 sclk xin xout tr cs reset clock output reset input trigger input test pin filter connect pin filter connect pin vco load output
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 2 of 14 pin arrangement (top view) M66238FP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 outline: 32p2w-a 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 digital gnd pin dgnd agnd agnd dgnd dgnd agnd agnd cpin cpout rv up tr down avcc avcc dvcc dvcc dgnd dvcc tcki tcko ckob vcco gndo pulse cko/pllo sin sclk xout xin reset cs reset input chip select input serial data input serial clock input digital power supply pin analog gnd pin analog gnd pin vco load output filter connect pin test pin trigger input filter connect pin analog gnd pin analog gnd pin digital gnd pin digital gnd pin analog power supply pin analog power supply pin digital power supply pin digital power supply pin sync output power supply pin sync output gnd pin one-shot pulse output clock output clock input test pin pll output clock output digital gnd pin pin description pin name name i/o function reset reset input input initializ e m66238 internal status. cs chip select input input transfer serial data when cs = "l". sin serial data input input synchronize 32-bit serial data from mcu with sck, and enter. sclk serial clock input input enter a sy nc clock for writing 32-bit serial data. xin clock input input xout clock output output used by connecting crystal oscillator between xin and xout. when using an external clock signal, connect the clock oscillator to xin pin and open xout pin. tr trigger input input trigger input for clock sync. ckob clock output output ou tput an inverted cko signal. cko/pllo pll output output cko outputs a clock synchronized with a trigger signal and pllo outputs a pll oscillator clock as it is. pulse one-shot pulse output ou tput output a one-shot pulse synchronized with a cko signal. cpout filter connect pin output connect a low pass filter to charge pump output. cpin filter connect pin input low pass filter input pin. rv vco load output output connect a load resistor for vco circuit operation between rv and gnd. tcki test pin input shipping test pin. connect to gnd when use. tcko test pin output shippi ng test pin. keep open when use. up test pin output shipping test pin. keep open when use. down test pin output shippi ng test pin. keep open when use. dvcc digital power supply pin ? digital power supply pin. dgnd digital gnd pin ? digital gnd pin. vcco sync output power supply pin ? power supply pin for sync output. gndo sync output gnd pin ? gnd pin for sync output. avcc analog power supply pin ? analog power supply pin. agnd analog gnd pin ? analog gnd pin.
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 3 of 14 absolute maximum ratings item symbol ratings unit supply voltage vcc ?0.5 to +7.0 v input voltage vi ?0.5 to vcc + 0.5 v output voltage vo ?0.5 to vcc + 0.5 v power dissipation * 1 pd 650 mw storage temperature tstg ?65 to +150 c note: 1. when board is mounted all voltages adopt the gnd pin of the circuit as the base (0 v) and abs olute values are displayed for maximum and minimum values. recommended operating conditions (ta = 0 to 70 c) item symbol min typ max unit supply voltage vcc 4.75 5 5.25 v supply voltage gnd ? 0 ? v input voltage vi 0 ? vcc v output voltage vo 0 ? vcc v operating ambient tem perature topr 0 ? 70 c note: the direction of current flowing into a circuit is defi ned to be positive (no sign) and the direction of current flowing out is defined to be negative (?sign). absolute values are displayed for maximum and minimum values. electrical characteristics (ta = 0 to 70 c, vcc = 5 v 5%, gnd = 0 v) item symbol min typ max unit test conditions high-level input voltage vih 2 ? ? v low-level input voltage vil ? ? 0.8 v tr high-level input voltage vih 0.8 vcc ? ? v low-level input voltage vil ? ? 0.2 vcc v xin high-level output voltage voh vcc ? 0. 8 ? ? v gnd = 0 v, ioh = ?4 ma low-level output voltage vol ? ? 0.55 v gnd = 0 v, iol = 4 ma supply current (at time of standstill) icc (s) ? ? 50 a gnd = 0 v, vi = vcc or gnd supply current (at time of operation) icc (a) ? ? 120 ma gnd = 0 v, cko = 50 mhz vi = vcc or gnd high-level input current iih ? ? 10 a gnd = 0 v, vi = vcc low-level input current iil ? ? ?10 a gnd = 0 v, vi = 0 v input capacitance ci ? ? 10 pf note: measurement circuit; the direction of current flowi ng to the circuit is specified to be positive (no sign).
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 4 of 14 timing requirements (ta = 0 to 70 c, vcc = 5 v 5%, gnd = 0 v) item symbol min typ max unit cs width tw ( cs ) 1 ? ? s cs set up time tsu ( cs -sck) 50 ? ? ns cs hold time th (sck- cs ) 50 ? ? ns sck width tw (sck) 25 ? ? ns sin set up time tsu (sin-sck) 25 ? ? ns sin hold time th (sck-sin) 25 ? ? ns clock input frequency fin 7 ? 12 mhz clock input duty fiduty 40 ? 60 % trigger input "h" pulse width tw (tr) 200 ? ? ns clock input rising time tr ? ? 5 ns clock input falling time tf ? ? 5 ns switching characteristics (ta = 0 to 70 c, vcc = 5 v 5%, gnd = 0 v, cl = 15 pf) item symbol min typ max unit vco oscillation frequency fvco 25 ? 50 mhz synchronous output frequency fout ? ? 50 mhz synchronous accuracy (jitter) ? t ? ? 3 ns synchronous clock output start tss (cko) ? ? tlp + 200 ns synchronous clock reversible output start tss (ckob) ? ? tlp + 200 ns one-shot pulse output start tss (pulse) ? ? tlp + 200 ns synchronous clock output stop tsp (cko) ? ? 40 ns synchronous clock reversible out put stop tsp (ckob) ? ? 40 ns one-shot pulse output width tw (pulse) n ? tp ? 10 ? n ? tp + 10 ns synchronous clock output duty fo duty (cko) 40 ? 60 % synchronous clock reversible output duty fo dut (ckob) 40 ? 60 % note: tp = 1 / fout, tlp = tp (100 ? fvcoduty) / 100 the n value of one-shot pulse output width is set in the register. measurement circuit input zo cl output v cc pg tested element notes: ? waveform for switching test input pulse level xin: 0 to vcc, tr: 0 to 3 v input pulse rising time: 3 ns input pulse falling time: 3 ns zo: 50 ? decision voltage input voltage xin: vcc/2, tr: 1.3 v output voltage all outputs: vcc/2 ? electrostatic capacitance: cl includes floating capacitance of connection and probe input capacitance.
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 5 of 14 list of register setting commands a1 a0 setting 0 0 setting of cko/pllo dividing ratio, pll sy nthesizer 15-bit generation dividing ratio and reference clock generation 12-bit dividing ratio. 1 0 setting of one-shot pulse polarity and width, setting of trigger edge, halt of entire m66238, halt of charge pump and vco, phase comparator output up/down, cko/pllo switching. 1 1 dummy trigger generation command serial data write timing cs sclk sin address bit a0 a1 d0 d1 d2 d3 d4 d5 d6 d26 d27 d28 d29 data bit
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 6 of 14 register configuration 1. clock frequency setting command reference clock generation 12-bit division ratio, pll synthe sizer 15-bit division ratio and cko/pllo division ratio are set at address (a1, a0) = (0, 0). data bit description default 0 d0 1 0 0 d1 1 1 0 d2 1 0 0 d3 1 1 0 d4 1 0 0 d5 1 0 0 d6 1 0 0 d7 1 0 0 d8 1 1 0 d9 1 0 0 d10 1 0 0 d11 1 12-bit reference clock dividing ratio is set. d11 and d0 correspond to msb and lsb, respectively. k = (dk 2 k ) k = 0 11 k: reference clock dividing ratio 0 0 d12 1 0 0 d13 1 0 0 d14 1 0 0 d15 1 1 0 d16 1 0 0 d17 1 1 0 d18 1 1 0 d19 1 1 0 d20 1 1 0 d21 1 1 0 d22 1 0 0 d23 1 0 0 d24 1 0 0 d25 1 0 0 d26 1 15-bit pll synthesizer dividing ratio is set. d26 and d12 correspond to msb and lsb, respectively. n = (dn 2 n-12 ) n = 12 26 n: pll synthesizer dividing ratio 0
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 7 of 14 data bit description default 0 d27 1 0 0 d28 1 1 0 d29 1 setting of cko/pllo dividing ratios dividing ratio d29 d28 d27 pll o/cko oscillator frequency 1/1 0 0 0 25 mhz to 50 mhz 1/2 0 0 1 12.5 mhz to 25 mhz 1/4 0 1 0 6.25 mhz to 12.5 mhz 1/8 0 1 1 3.125 mhz to 6.25 mhz 1/16 1 0 0 1.563 mhz to 3.125 mhz 1/32 1 0 1 0.781 mhz to 1.563 mhz 0
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 8 of 14 2. operating mode setting commands address (a1, a0) = (1, 0) allows setting of one-shot pul se polarity and width, trigger edge, m66238 entire halt, charge pump and vco halt, phase comparator up/down output, lpf cutoff, cko/pllo switching, vco switching and charge pump switching. data bit description default 0 d0 1 0 0 d1 1 setting of trigger edge d1 d0 description 0 0 synchronizes with tr cko is stopped when tr = "h" 0 1 synchronizes with tr cko is stopped when tr = "l" 1 0 synchronizes with tr cko is output when tr = "h" 1 1 synchronizes with tr cko is output when tr = "l" 0 0 when trigger occurs: spike of sync clock is not eliminated. d2 1 when trigger occurs: spike of sync clock is eliminated (disabled when d1 = 1). 0 0 polarity of one-shot pulse: negative pulse d3 1 polarity of one-shot pulse: positive pulse 0 0 d4 1 0 0 d5 1 setting of one-shot pulse width d5 d4 description 0 0 cko 2-cycle width 0 1 cko 4-cycle width 1 0 cko 8-cycle width 1 1 cko 16-cycle width 0 0 cko/pllo pin: cko output d6 1 cko/pllo pin: pllo output 0 0 entire m66238: operating state d7 1 entire m66238: halt state 0 0 vco: operating state d8 1 vco: halt state 0 0 charge pump: on d9 1 charge pump: off 0 0 low pass filter: operating state d10 1 low pass filter: separated 0 0 normal use: not output to outside d11 1 phase comparator up/down output enable 0 0 normal use d12 1 vco test circuit set 0 0 normal use d13 1 charge pump test circuit set 0 0 normal use d14 1 15-bit counter test clock enable 0 0 normal use d15 1 sync clock generator test clock enable 0 0 normal use d16 1 sync clock generator test input enable 0 0 normal use d17 1 12-bit counter test output enable 0 0 normal use d18 1 15-bit counter test output enable 0 0 normal use d19 1 sync clock generator trigger test output enable 0 0 normal use d20 1 sync clock generator test output enable 0 d21 : d29 in normal use: "0" set 0 : 0
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 9 of 14 3. dummy trigger generating command the internal status of sync clock generator becomes unsta ble and a stable sync clock output (cko) is not obtained after the power is turned on, after a reset is cleared or after an internal vco oscillator frequency is set. to obtain a stable sync clock output, enter a tri gger signal from the tr input after vco oscillator becomes stable, or enter a dummy trigger generating command from the mcu. the pll synthesizer oscillator frequency after the cancellation of a reset depends on a default (see the register configuration). set the command for address (a1, a0) = (1, 1). data bit description default 0 d0 1 the command must be stored two times continuously when a dummy trigger is generated. for the first time, set the dummy trigger generating command with d0 = 1. for the second time, set the dummy trigger generating command with d0 = 0. the second setting becomes a sync edge and a clock begins to be output from cko. after the first setting, cko is in the halt state. 0 0 d1 1 0 0 d29 1 in normal use: "0" 0 operating timing 1. sync clock spike non-removal mode upon occurrence of trigger 1.1 setting of trigger edge when d1 = 0 one-shot pulse start timing: 1st leading edge of cko after tr fall one-shot pulse polarity: negative pulse one-shot pulse width: 16 cycles of cko cko output dividing ratio: 1/2 division an example set for the condition of address (a1, a0) = (1, 0), data (d6, d5, d4, d3, d2, d1, d0) = (0, 1, 1, 0, 0, 0, 0) is shown below. cko is a clock output synchronized by tr and pulse is a one-shot pulse synchronized with the rise of cko. internal vco oscillator clock tp = 1 / fvco tp = 1 / fout tlp tw (tr) tsp (cko) tss (cko) tw (pulse) tss (pulse) spike ? t ? t tr cko pulse
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 10 of 14 1.2 setting of trigger edge when d1 = 1 one-shot pulse start timing: 1st leading edge of cko after tr rise (except the rise of a spike which occurs when cko is stopped). one-shot pulse polarity: negative pulse one-shot pulse width: 16 cycles of cko cko output dividing ratio: 1/2 division an example set for the condition of address (a1, a0) = (1, 0), data (d6, d5, d4, d3, d2, d1, d0) = (0, 1, 1, 0, 0, 1, 0) is shown below. cko is a clock output synchronized by tr and pulse is a one-shot pulse synchronized with the rise of cko. internal vco oscillator clock tp = 1 / fvco tp = 1 / fout tlp tw (tr) tsp (cko) tss (cko) tw (pulse) spike ? t ? t tr cko pulse 2. sync clock spike removal mode upon occurrence of trigger when address (a1, a0) = (1, 0) and data (d6, d5, d4, d3, d2, d1, d0) = (0, 1, 1, 0, 1, 0, 0), cko with the first rise after occurrence of a trigger is output and then cko stops. however, this mode is not available when d1 = 1 in trigger e dge setting. set a wide tr so that tr sync edge is entered 200 ns or more after cko stops. tr tw (tr) 200 ns or more required 1st tss (cko) tss (ckob) tss (pulse) tw (pulse) ? t ? t ? t cko ckob pulse notes: 1. 200 ns or more required 2. tss (cko, ckob, pulse) is defined by input clock width "l" + . in addition, the value of denotes ic internal delay, and the values of and tss are definite unless temperatur e, vcc, etc. are changed, and tss variations at that time is defined as ? t (sync accuracy: jitter).
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 11 of 14 cko/pllo output frequency range the m66238 requires an internal vco osc illator frequency of 25 mhz to 50 mhz. settings of dividing ratio k of 12-bit divider and dividing ra tio n of 15-bit counter are required in order to determine the internal vco oscillator frequency. the relation between the settings and the internal vco oscillator frequency is shown below. oscillator frequency k 11 k = 0 f vco = (mhz) k = (d k 2 k ) fin n 26 n = 12 n = (d n 2 n ? 12 ) note: 3. setting of fin / k 100 khz is recommended in consideration of the frequency accuracy characteristics of pll output. therefore, set the division ratio k of the 12-bit divider and the division ratio n of the 15-bit counter to meet the following conditions: 25 mhz fvco 50 mhz in addition, for pllo and cko, setting the division ra tios of the sync/division circuit (synchronous clock generating area) to 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 will allow the frequencies of 0.78 hz to 50 mhz to be accommodated.
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 12 of 14 input timing (1) register setting cs sck tsu ( cs -sck) tw ( cs ) th (sck- cs ) tw (sck) tsu (sin-sck) th (sck-sin) tw (sck) 50% 50% 50% 50% v cc 0 v v cc 0 v v cc 0 v 50% 50% sin (2) clock from trigger input and one-shot pulse output tss 0 v voh vol 3 v 1.3 v 50% tr cko ckob pulse (3) stop of clock from trigger input 0 v voh vol 3 v tsp 1.3 v 50% tr cko ckob (4) trigger input width 0 v 3.0 v tw (tr) 1.3 v 1.3 v tr (5) one-shot pulse width voh vol tw (pulse) 50% 50% pulse
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 13 of 14 application circuit example digital power supply programmable interface 30 pf 30 pf crystal oscillator digital gnd M66238FP nc nc analog power supply analog gnd programmable interface 7.5 k ? 2 k ? 1.2 k ? 0.015 f nc 1 m ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
M66238FP rej03f0268-0200 rev.2.00 mar 18, 2008 page 14 of 14 package dimensions sop32-p-450-1.27 weight(g) ? jedec code 0.67 eiaj package code lead material alloy 42 32p2w-a plastic 32pin 450mil sop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 ? ? 0.35 0.05 0.13 19.8 8.2 11.63 0.3 1.27 ? ? ? ?? ?? ?? 2.0 0.4 0.15 20.0 8.4 1.27 11.93 0.5 1.765 11.43 ? ?? ? ?? ?? ?? ?? ?? .4 2 0.5 0.2 20.2 8.6 12.23 0.7 0.15 b 2 0.76 0 10 e e 1 32 17 16 1 h e e d e f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g x z 1 0.475 0.625 0.25 z g y b x m
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